vhdl/verilog code 삽입 방법

vhdl 코드나 verilog 코드 삽입이 쉽지 않아서 삽질을 많이 했습니다..

 

1. 코드블럭 삽입 ->

2. 코드 작성(언어 아무거나 상관 x)

3. 기본모드를 HTML 모드로 변경

4. class="verilog" data-ke-language="verilog"  <- verilog 작성 시

    class="vhdl" data-ke-language="vhdl"  <- vhdl 작성 시

5. 기본모드로 변경

 

여기저기 짜집기를 많이해서 이것말고도 더 셋팅을 해서 된걸수도 있는데... 일단 저는 위 방법으로 했습니다!!

 

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date: 2023/01/05 21:58:58
-- Design Name: 
-- Module Name: test_led_sw - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
----------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity test_led_sw is
Port(
    sysclk : in std_logic;
    sw : in std_logic_vector(3 downto 0);
    btn : in std_logic_vector(3 downto 0); --btn (3) rst, btn default value : 0
    led : out std_logic_vector(3 downto 0);
    led6_r : out std_logic;
    led6_g : out std_logic;
    led6_b : out std_logic
);
end test_led_sw;

architecture Behavioral of test_led_sw is
signal s_sw : std_logic_vector(3 downto 0) := (others =>'0');
signal s_btn : std_logic_vector(3 downto 0) := (others =>'0');

signal s_led : std_logic_vector(3 downto 0) := (others =>'0');
signal s_led6_r : std_logic := '0'; -- '1' : led_on 
signal s_led6_g : std_logic := '0';
signal s_led6_b : std_logic := '0';

begin
led <= s_led;
led6_r <= s_led6_r;
led6_g <= s_led6_g;
led6_b <= s_led6_b;

process(btn(3),sysclk)
begin
    if(btn(3) = '1')then
		s_sw <= (others => '0');
        s_btn <= (others => '0');
    elsif(sysclk'event and sysclk = '1')then
        s_sw <= sw; -- input sw sync
        s_btn <= btn; --input btn sync     
    else
        s_sw <= s_sw;
        s_btn <= s_btn;
    end if;
end process;

process(btn(3),sysclk)
begin
    if( btn(3) = '1' )then
		s_led <= (others => '0');
    elsif(sysclk'event and sysclk = '1')then
		s_led <= s_sw;
    else
		s_led <= s_led;
    end if;
end process;

process(btn(3),sysclk)
begin
    if( btn(3) = '1' )then
        s_led6_r <= '0';
        s_led6_g <= '0';
        s_led6_b <= '0';
    elsif(sysclk'event and sysclk = '1')then
        s_led6_r <= s_btn(0);
		s_led6_g <= s_btn(1);
		s_led6_b <= s_btn(2);
    else
        s_led6_r <= s_led6_r;
        s_led6_g <= s_led6_g;
        s_led6_b <= s_led6_b;
    end if;
end process;

end Behavioral;